1. Technical Field
The present disclosure relates to a method for writing and reading data in an electrically erasable and programmable nonvolatile memory such as an EEPROM memory or a Flash memory and, more particularly, to writing and reading data in an electrically erasable and programmable nonvolatile memory in order to protect the memory against the loss of data due to a power interruption.
2. Description of the Related Art
Conventionally, the recording of updating data in a target location of an electrically erasable and programmable nonvolatile memory involves a step of erasing the memory cells of the target location and then a step of writing all or part of these memory cells. The erase step allows for setting all the memory cells of the target location in an erased state corresponding to a first logic value which is defined by convention, for example “1”. The write step, also called “programming”, allows for setting certain memory cells in a programmed state corresponding, when the memory cells are read, to a second logic value, for example “0”. Therefore, the write step is only applied to memory cells that must receive the second logic value and is always preceded by the erase step that is applied to all memory cells of the target location.
In a conventional electrically erasable and programmable nonvolatile memory, updating data that must be written in the memory are stored in a volatile buffer during the erasure of the target location. Therefore, a power interruption occurring either during the erasure of the target location or after the erasure of the target location and before updating data have been written in the memory results in an irretrievable loss of the initial data present in the target location and of the updating data present in the volatile buffer. The memory cells that contained the initial data are erased or are in an undetermined state, and the volatile memory has lost the updating data since it is no longer powered.
Now, some applications are such that the continuity of the power supply cannot be guaranteed. In particular, nonvolatile memories can be embedded in portable electronic devices such as chip cards and electronic tags that, due to portability and size constraints, do not include a power-supply source. For this reason, chip cards and electronic tags are typically powered by an external device such as a chip card reader when data are read from or written into their memory. This power supply can be interrupted at any moment, for example if the user suddenly tears a chip card from the slot in which it is inserted or tears a contactless card or a contactless tag from the magnetic field from which the power supply is extracted.
Consequently, the use of conventional electrically erasable and programmable nonvolatile memories in applications where there is a high risk of a power interruption makes the erase/write process unreliable.
Some recent developments have provided methods for writing such nonvolatile memories so as to prevent data loss during the erase/write process, in case of power interruption. These write methods are generally called “anti-tearing” methods because they aim to protect data against power interruption that are often caused by a tearing action by the user, in applications that have been mentioned above.
For example, it has been proposed to provide a backup memory location into which the initial page data are transferred before the target page location is erased. The page data are then updated and rewritten into the target page location and the backup location is erased.
Other known methods provide a pre-erased nonvolatile buffer into which the content of updated pages are written while the initial pages are kept in their initial states.
In particular, the U.S. Patent Publication No. 2004/0114431 discloses a Flash memory that includes a buffer divided into sectors. During a write operation, updating data to be written in a target sector in the Flash memory, as well as the address of the target sector, are written into an erased sector of the buffer. Erasure of buffer sectors following the sector that received the updating data and erasure of the target sector in the Flash memory is then performed using a rolling method that includes N steps of partial erasure.
In U.S. Patent Publication No. 2005/0251643, a main nonvolatile memory includes a further memory page and an address translation unit. The address translation unit maps logical addresses to physical addresses of the main nonvolatile memory or of the further memory page. During the write process, a new data element and the initial content of a page are written as updated page data into the further memory page, and then the initial page is erased. A counter is used to indicate which logical address includes the most-recently updated data. The updated page is then written into an erased area in the main memory, and the address translation unit re-maps the new physical address of the updated page to the previous logical address, and then the further memory page is erased.
In summary, conventional “anti-tearing” methods protect the initial page data or sector data present in the memory by allowing the updated page or sector data to be written in an erased location different from that of the target location without necessitating the prior erasure of the initial page or sector data. A correspondence table or address translation unit allows, when the target page or sector is to be read, the location of the most-recently updated page or sector data to be found.
However, some electrically erasable and programmable memories have a different “atomicity” with respect to, on the one hand, the smallest data element or “atomic unit of data” that can be individually written and, on the other hand, the smallest memory area that can be individually erased. For example, Flash memories generally differ from EEPROM memories in that they are generally page-erasable or sector-erasable whereas numerous EEPROM memories are word-erasable. Since a page generally contains a high number of words (a word is an X-bit data string with “X” depending upon the architecture of the memory), the writing of an updating word requires that the entire target page intended to receive the updating word be first completely erased.
Therefore, conventional “anti-tearing” methods require that updating data are first combined with other initial page data or sector data in order to obtain an updated version of the page or of the sector. The updated version of the page or of the sector is then written in an erased location different from that of the target page or target sector location. This means that a significant memory space is necessary to perform the “anti-tearing” write process. For example, in a page-erasable Flash memory wherein each page contains 256 words, writing a single word requires that a complete page location first be erased and then that a complete updated version of the page, including the updated word, be written. In addition, Flash memories have a limited number of write erase cycles that they can reliably perform, typically 100,000 cycles per page. If only one byte is being updated, the entire page must be cycled, resulting in a shorter lifespan.